Effective Controller in Optimized Asynchronous Logic

Asynchronous Fine-grain power gated Logic (AFL) which includes Modified Efficient Charge Recovery Logic (M-ECRL) gates to implement the logic function of the stage with a handshake controller which comprises of C-element to handle the control signals with the neighboring stages and provides power to MECRL gate. AFL adopts an partial charge reuse (PCR) mechanism, part of the charge on the output nodes of MECRL gate which entering the discharge phase can be used to charge the output nodes of another M-ECRL gate which is more enough to complete evaluate phase, thus reducing the power consumption. To design the efficient asynchronous styles with effective controller from their available CMOS topology. Moreover, study is to scrutinize the use of different controller implementations in a single design in order to generate hybrid and optimized designs. Index terms Asynchronous circuits, logic gates, lowpower electronics, power gating.